L6569 L6569A
Bootstrap Function
The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in sim-
ilar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the
Upper External Mosfet.
The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven
by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side
Gate driver (LVG pin), actually working as a synchronous rectifier .
The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG
High) for a time interval:
T
C
= R
F
· C
F
· In2
→
1.1 · R
F
· C
F
starting from the time the Supply Voltage V
S
has reached the Turn On Voltage (V
SUVP
= 9 V typical value).
After time T
1
(see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a R
ON
=120
Ω
(typical value).
In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is
drive OFF until V
S
has reached the Turn On Threshold (V
SUVPp
), then again the T
C
time interval starts as above.
Being the LDMOS used to implement the bootstrap operation a ”bi-directional” switch the current flowing into
the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING opera-
tions is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example,
when the load is removed and an high resistive value is placed in series with the gate of the external Power
Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided
(fig. 7).
Let’s consider the steps that should be taken.
1) Calculate the Turn on delay ( td ) of your Lower Power MOS:
1
---------
t
d
=
(
R
g
+
R
id
) ⋅
C
iss
⋅
ln
---------- -
V
T H
-
1
– ----------
V
S
2) Calculate the Fall time ( tf ) of your Lower Power MOS:
R
g
+
R
id
-
t
f
= -----------------------
⋅
Q
gd
V
S
–
V
T H
where:
R
g
= External gate resistor
R
id
= 50
Ω
, typical equivalent output resistance of the driving buffer (when sourcing current)
V
TH
, C
iss
and Q
gd
are Power MOS parameters
V
S
= Low Voltage Supply.
3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS
(remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example
is given where:
V
S
= Low Voltage Supply
V
HV
= High Voltage Supply Rail
The V
BOOT
voltage swing must fall below the curve identified by the actual operating frequency of your applica-
tion.
5/13
STMICROELECTRONICS [ STMICROELECTRONICS ]
