L6562A
Application information
Figure 3. THD optimization: standard TM PFC controller (left side) and L6562A
(right side)
Input current
Input current
Rectified mains voltage
Rectified mains voltage
Imains
Input current
Imains
Input current
Vdrain
MOSFET's drain voltage
Vdrain
MOSFET's drain voltage
To overcome this issue the circuit embedded in the device forces the PFC pre-regulator to
process more energy near the line voltage zero-crossings as compared to that commanded
by the control loop. This will result in both minimizing the time interval where energy transfer
is lacking and fully discharging the high-frequency filter capacitor after the bridge. The effect
of the circuit is shown in figure 2, where the key waveforms of a standard TM PFC controller
are compared to those of the L6562A.
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid.
To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after
the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -
even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the
optimizer circuit little effective.
11/20
STMICROELECTRONICS [ ST ]
