HCF4017B
TYPICAL APPLICATIONS
DIVIDE BY N COUNTER(N
DECODED OUTPUTS
When the N
th
decoded output is reached (N
th
clock pulse) the S-R flip-flop (constructed from two
NOR gates of the HCF4001B) generates a reset
pulse which clears the HCF4017B to its zero
count. At this time, if the N
th
decoded output is
greater than or equal to 6, the C
OUT
line goes high
to clock the next HCF4017B counter section. The
"0" decoded output also goes high at this time.
Coincidence of the clock low and decoded "0"
output high resets the S-R flip-flop to enable the
HCF4017B. If the N
th
decoded output is less than
6, the COUT line will not go high and, therefore,
cannot be used. In this case "0" decoded output
may be used to perform the clocking function for
the next counter.
<
10)
WITH
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200KΩ
R
T
= Z
OUT
of pulse generator (typically 50Ω)
6/11
STMICROELECTRONICS [ STMICROELECTRONICS ]
