ST24/25C04, ST24/25W04
DEVICE OPERATION
(cont’d)
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode.
In all read modes
the ST24/25x04 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x04 terminate the
data transfer and switches to a standby state.
Figure 11. Read Modes Sequence
ACK
CURRENT
ADDRESS
READ
DEV SEL
NO ACK
DATA OUT
START
R/W
ACK
RANDOM
ADDRESS
READ
DEV SEL *
ACK
DEV SEL *
STOP
ACK
NO ACK
DATA OUT
BYTE ADDR
START
START
R/W
R/W
ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
ACK
ACK
NO ACK
DATA OUT 1
R/W
DATA OUT N
START
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
ACK
DEV SEL *
ACK
ACK
BYTE ADDR
DATA OUT 1
START
R/W
START
R/W
ACK
NO ACK
DATA OUT N
STOP
AI00794C
Note:
* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
12/16
STOP
STOP
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