Current @
TS
Pin
Input Bias
Current @
CS Pin
Output
Voltage
Current
Regulation
Threshold
Current
Detect
Threshold
Precharge
Threshold
Recharge
Threshold
Charge
Teminated
Current
Detect
Threshold
Ouput Low
Voltage
@STAT1Pin
Ouput High
Voltage
@STAT1Pin
Ouput Low
Voltage
@STAT2 Pin
Ouput High
Voltage
@STAT2 Pin
Lower
Temperature
Threshold
Upper
Temperature
Threshold
I
CS
V
BATT
-V
DD
≥0.2V
V
CS
=5V,
V
BATT
-V
DD
≥0.2V
---
---
1.1
uA
V
O(REG)
V
I(SNS)
V
I(SNS)
=V
DD
-V
CS
4.160
100
4.20
115
4.240
130
V
mV
V
(PRE)
V
(PRE)
=V
DD
-V
CS
4
12
24
mV
V
O(MIN)
V
O(RCH)
V
(TERM)
V
(TERM)
=V
DD
-V
CS
2.7
V
O(REG)
-
170mV
2
2.9
V
O(REG)
-
110mV
12
3.1
V
O(REG)
-
50mV
22
V
V
mV
V
STAT1(LOW)
I
OL
=10mA
-----
0.4
0.6
V
V
STAT1(HIGH)
I
OH
=5mA
V
DD
-0.5V
----
----
V
V
STAT2(LOW)
I
OL
=10mA
-----
0.4
0.6
V
V
STAT2(HIGH)
I
OH
=5mA
V
DD
-0.5V
----
----
V
V
TS1*
28
30
32
%V
DD
V
TS2*
68
70
72
%V
DD
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage
to the device. These are for stress ratings. Functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for
4