FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
Expanded RAM Access (Indirect Addressing only):
address bits. This provides external paging capabilities.
Using MOVX @DPTR generates a 16-bit address. This
allows external addressing up the 64K. Port 2 provides the
high-order eight address bits (DPH), and Port 0 multiplexes
the low order eight address bits (DPL) with data. Both
MOVX @Ri and MOVX @DPTR generates the necessary
read and write signals (P3.6 - WR# and P3.7 - RD#) for
external memory use. Table 3-3 shows external data mem-
ory RD#, WR# operation with EXTRAM bit.
MOVX
@DPTR, A
; DPTR contains 0A0H
DPTR points to 0A0H and data in “A” is written to address
0A0H of the expanded RAM rather than external memory.
Access to external memory higher than 2FFH using the
MOVX instruction will access external memory (0300H to
FFFFH) and will perform in the same way as the standard
8051, with P0 and P2 as data/address bus, and P3.6 and
P3.7 as write and read timing signals.
The stack pointer (SP) can be located anywhere within the
256 bytes of internal RAM (lower 128 bytes and upper 128
bytes). The stack pointer may not be located in any part of
the expanded RAM.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will
be similar to the standard 8051. Using MOVX @Ri pro-
vides an 8-bit address with multiplexed data on Port 0.
Other output port pins can be used to output higher order
TABLE
3-3: External Data Memory RD#, WR# with EXTRAM bit
MOVX @DPTR, A or MOVX A, @DPTR
MOVX @Ri, A or MOVX A, @Ri
ADDR = Any
AUXR
ADDR < 0300H
RD# / WR# not asserted
RD# / WR# asserted
ADDR >= 0300H
EXTRAM = 0
EXTRAM = 1
RD# / WR# asserted
RD# / WR# asserted
RD# / WR# not asserted1
RD# / WR# asserted
T3-3.0 1273
1. Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
14
SST [ SILICON STORAGE TECHNOLOGY, INC ]
