32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V
DD
via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ
6
will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
6
will
toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
2
)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 7 for Toggle Bit timing dia-
gram and Figure 20 for a flowchart.
TABLE 1: W
RITE
O
PERATION
S
TATUS
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
DQ
7
DQ7#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
RY/BY#
0
0
1
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
IH
) the device is in x16 data configuration: all
data I/0 pins DQ
0
-DQ
15
are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ
0
-DQ
7
are active and con-
trolled by CE# and OE#. The remaining data pins DQ
8
-
DQ
14
are at Hi-Z, while pin DQ
15
is used as the address
input A
-1
for the Least Significant Bit of the address bus.
Data# Polling (DQ
7
)
When the devices are in an internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
(DQ
7
) timing diagram and Figure 20 for a flowchart.
Data
Data
Data
1
DQ7#
Toggle
N/A
0
T1.1 1270
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
Data Protection
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
