256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF256
Symbol Parameter
Min
1
Max
Units
µs
TAS
Address Setup Time
Address Hold Time
TAH
1
µs
TPRT
TVPS
TVPH
TPW
TEW
TDS
VPP Pulse Rise Time
VPP Setup Time
50
1
ns
µs
VPP Hold Time
1
µs
CE# Program Pulse Width
CE# Erase Pulse Width
Data Setup Time
20
100
1
30
µs
500
ms
µs
TDH
TVR
Data Hold Time
1
µs
VPP and A9 Recovery Time
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
1
µs
TART
TA9S
TA9H
50
1
ns
µs
1
µs
T14.0 502
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF512
Symbol Parameter
Min
1
Max
Units
µs
TAS
Address Setup Time
TAH
Address Hold Time
1
µs
TPRT
TVPS
TVPH
TPW
TEW
TDS
OE#/VPP Pulse Rise Time
OE#/VPP Setup Time
50
1
ns
µs
OE#/VPP Hold Time
1
µs
CE# Program Pulse Width
CE# Erase Pulse Width
Data Setup Time
20
100
1
30
µs
500
ms
µs
TDH
TVR
Data Hold Time
1
µs
OE#/VPP and A9 Recovery Time
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
1
µs
TART
TA9S
TA9H
50
1
ns
µs
1
µs
T15.0 502
TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF010/020
Symbol Parameter
Min
1
1
1
1
Max
Units
µs
µs
µs
µs
TCES
TCEH
TAS
CE# Setup Time
CE# Hold Time
Address Setup Time
Address Hold Time
TAH
TPRT
TVPS
TVPH
TPW
TEW
TDS
VPP Pulse Rise Time
VPP Setup Time
VPP Hold Time
PGM# Program Pulse Width
PGM# Erase Pulse Width
Data Setup Time
50
1
1
20
100
1
ns
µs
µs
µs
ms
µs
30
500
TDH
Data Hold Time
1
µs
TVR
A9 Recovery Time for Erase
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
1
50
1
µs
ns
µs
µs
TART
TA9S
TA9H
1
T16.0 502
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01 502
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
