Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
Pin Description
CE#
SO/SIO1
SIO2
VSS
1
2
8
7
VDD
SIO3
SCK
SI/SIO0
CE#
SO/SIO1
SIO2
VSS
1
8
VDD
SIO3
SCK
SI/SIO0
2
7
Top View
3
4
6
5
3
Top View
6
4
5
1359 08-soic S2A P1.0
1359 08-wson QA P1.0
8-Lead SOIC
8-Contact WSON
Figure 2:
Pin Description for 8-lead SOIC and 8-contact WSON
Table 1:
Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the
clock input, while output data is shifted out on the falling edge of the clock
input.
To transfer commands, addresses, or data serially into the device or data out
of the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The EQIO command
instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a
power on reset.
SIO[3:0]
Serial Data
Input/Output
SI
Serial Data Input
for SPI mode
SO
CE#
Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling
for SPI mode
edge of the serial clock. SO is the default state after a power on reset.
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain
low for the duration of any command sequence; or in the case of Write oper-
ations, for the command/data input sequence.
To provide power supply voltage: 2.7-3.6V
T1.0 1359
V
DD
V
SS
Power Supply
Ground
©2010 Silicon Storage Technology, Inc.
S71359-05-000
06/10
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
