Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
Table 3: Device Operation Instructions for SST26VF016/032 (Continued) (2 of 2)
Command
Cycle1
Address Dummy
Data
Maximum
Instruction
RBPR13
WBPR11,13
LBPR11
Description
Cycle(s)2 Cycle(s) Cycle(s) Frequency
Read Block Protection Register
Write Block Protection Register
72H
42H
8DH
0
0
0
0
0
0
1 to m/4
1 to m/4
0
80 MHz
Lock Down Block Protection
Register
T3.0 1359
1. One BUS cycle is two clock periods (command, access, or data).
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
4. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
5. After a power cycle, Read, High-Speed Read, and JEDEC-ID Read instructions input and output cycles are SPI bus
protocol.
6. Burst length– n = 8 Bytes: Data(00H); n = 16 Bytes: Data(01H); n = 32 Bytes: Data(02H); n = 64 Bytes: Data(03H).
7. Address is 256 Bytes page align (2’s complement)
8. The Quad J-ID read wraps the three Quad J-ID Bytes of data until terminated by a low-to-high transition on CE#
9. Sector Addresses: Use AMS - A12, remaining address are don’t care, but must be set to VIL or VIH
10. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS
.
-
A15 for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don’t care, but must be set to VIL or VIH
11. Requires a prior WREN command.
.
12. The Read-Status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
13. Data is written/read from MSB to LSB. MSB = 48 for SST26VF016; 80 for SST26VF032
No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other
command.
©2010 Silicon Storage Technology, Inc.
S71359-05-000
06/10
12
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