64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the Memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 4 describes the function of each bit in the software
status register.
TABLE 4: Status Register
Default at
Bit Name
Function
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
4
5
6
BP0
BP1
BP2
BP3
SEC1
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
1
1
R/W
R/W
R/W
R/W
R
1
1
01
Security ID status
1 = Security ID space locked
0 = Security ID space not locked
7
BPL
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are readable/writable
0
R/W
T4.0 1392
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; otherwise, the
default at power up is ‘0’.
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A ‘1’ for the Busy bit indi-
cates the device is busy with an operation in progress. A ‘0’
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
•
•
•
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Write-Status Register instruction completion
Page-Program instruction completion
Dual-Input Page-Program instruction completion
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Program SID instruction completion
Lockout SID instruction completion
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
7
SST [ SILICON STORAGE TECHNOLOGY, INC ]
