8 Mbit SPI Serial Flash
SST25LF080A
EOL Product Data Sheet
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A23-A0] and a dummy byte. CE# must
remain active low for the duration of the High-Speed-Read
cycle. See Figure 5 for the High-Speed-Read sequence.
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
8 Mbit density, once the data from address location
0FFFFFH has been read, the next output will be from
address location 000000H.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
80
71 72
SCK
0B
ADD.
ADD.
ADD.
X
SI
MSB
MSB
N
OUT
N+1
N+2
N+3
D
OUT
N+4
HIGH IMPEDANCE
D
OUT
D
D
D
OUT
SO
OUT
MSB
1248 F05.0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V or V
)
IH
IL
FIGURE 5: HIGH-SPEED-READ SEQUENCE
©2006 Silicon Storage Technology, Inc.
S71248-06-EOL
1/06
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