8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read.
The device outputs a data stream starting from the speci-
fied address location. The data stream is continuous
through all addresses until terminated by a low-to-high tran-
sition on CE#. The internal address pointer automatically
increments until the highest memory address is reached.
Once the highest memory address is reached, the address
pointer automatically increments to the beginning (wrap-
around) of the address space. For example, for 8 Mbit den-
sity, once the data from the address location FFFFFH is
read, the next output is from address location 000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits A23-A0. CE# must
remain active low for the duration of the Read cycle. See
Figure 7 for the Read sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63 64
70
24
32
SCK
MODE 0
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
N+1
N+2
N+3
N+4
D
D
D
D
D
OUT
SO
OUT
OUT
OUT
OUT
MSB
1203 F06.0
FIGURE 7: Read Sequence
High-Speed-Read (75 MHz)
The High-Speed-Read instruction supporting up to 75 MHz
Read is initiated by executing an 8-bit command, 0BH, fol-
lowed by address bits [A23-A0] and a dummy byte. CE#
must remain active low for the duration of the High-Speed-
Read cycle. See Figure 8 for the High-Speed-Read
sequence.
addresses until terminated by a low-to-high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. For example, for 2 Mbit den-
sity, once the data from address location 7FFFFH is read,
the next output will be from address location 000000H.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
80
71 72
SCK
SI
0B
ADD.
ADD.
ADD.
X
MSB
N
N+1
N+2
N+3
N+4
HIGH IMPEDANCE
D
D
D
D
D
SO
OUT
OUT
OUT
OUT
OUT
MSB
1203 F07.0
FIGURE 8: High-Speed-Read Sequence
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
10
SST [ SILICON STORAGE TECHNOLOGY, INC ]
