512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Hold
The Hold operation enables the hold pin functionality of the
RST#/HOLD# pin. Once set to hold pin mode, the RST#/
HOLD# pin continues functioning as a hold pin until the
device is powered off and then powered on. After a power-
off and power-on, the pin functionality returns to a reset pin
(RST#) mode. See “Enable-Hold (EHLD)” on page 20 for
detailed timing of the Hold instruction.
In the hold mode, serial sequences underway with the SPI
Flash memory are paused without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The Hold mode ends when the rising edge
of the HOLD# signal coincides with the SCK active low
state. If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device enters
Hold mode when the SCK next reaches the active low
state. Similarly, if the rising edge of the HOLD# signal does
not coincide with the SCK active low state, then the device
exits Hold mode when the SCK next reaches the active low
state. See Figure 5 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, the
device returns to standby mode. The device can then be
re-initiated with the command sequences listed in Tables 9
and 10. As long as HOLD# signal is low, the memory
remains in the Hold condition. To resume communication
with the device, HOLD# must be driven active high, and
CE# must be driven active low. See Figure 5 for Hold tim-
ing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1328 Fx5.0
FIGURE 5: Hold Condition Waveform
Write Protection
SST25WF512/010/020/040 provide software Write pro-
tection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-
Protection bits (BP2, BP1, BP0, and BPL) in the status reg-
ister provide Write protection to the memory array and the
status register. See Table 5 for the Block-Protection
description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1328
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
