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SST25VF080B-80-4I-QAE 参数 Datasheet PDF下载

SST25VF080B-80-4I-QAE图片预览
型号: SST25VF080B-80-4I-QAE
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位的SPI串行闪存 [8 Mbit SPI Serial Flash]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 32 页 / 752 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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8 Mbit SPI Serial Flash  
SST25VF080B  
Data Sheet  
Read (25/33 MHz)  
The Read instruction, 03H, supports up to 25 MHz (for  
increment to the beginning (wrap-around) of the address  
space. Once the data from address location 1FFFFFH has  
been read, the next output will be from address location  
000000H.  
SST25VF080B-50-xx-xxxx)  
or  
33  
MHz  
(for  
SST25VF080B-80-xx-xxxx) Read. The device outputs the  
data starting from the specified address location. The data  
output stream is continuous through all addresses until ter-  
minated by a low to high transition on CE#. The internal  
address pointer will automatically increment until the high-  
est memory address is reached. Once the highest memory  
address is reached, the address pointer will automatically  
The Read instruction is initiated by executing an 8-bit com-  
mand, 03H, followed by address bits [A23-A0]. CE# must  
remain active low for the duration of the Read cycle. See  
Figure 5 for the Read sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
39  
40  
47 48  
55 56  
63 64  
70  
24  
32  
SCK  
MODE 0  
03  
ADD.  
MSB  
HIGH IMPEDANCE  
ADD.  
ADD.  
SI  
MSB  
N
N+1  
N+2  
N+3  
N+4  
D
D
D
D
D
SO  
OUT  
OUT  
OUT  
OUT  
OUT  
MSB  
1296 ReadSeq_0.0  
FIGURE 5: Read Sequence  
©2010 Silicon Storage Technology, Inc.  
S71296-04-000  
01/10  
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