64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
INSTRUCTIONS
Instructions are used to read, write (Erase and Program),
and configure the SST25VF064C. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. The Write-Enable (WREN) instruction must be
executed prior any Page-Program, Dual-Input Page-Pro-
gram, Sector-Erase, Block-Erase, Write-Status-Register,
Chip-Erase, Program SID, or Lockout SID instructions. The
complete list of instructions is provided in Table 6.
All instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of SCK
starting with the most significant bit. CE# must be driven
TABLE 6: Device Operation Instructions
Instruction
Read
Fast-Read Dual I/O
Fast-Read Dual-Output
High-Speed Read
Sector-Erase
4
32 KByte Block-Erase
5
64 KByte Block-Erase
6
Chip-Erase
Page-Program
Dual-Input Page-
Program
RDSR
7
EWSR
WRSR
WREN
WRDI
RDID
8
JEDEC-ID
EHLD
Read SID
Program SID
9
Lockout SID
9
1.
2.
3.
4.
low before an instruction is entered and must be driven
high after the last bit of the instruction has been shifted in
(except for Read, Read-ID, and Read-Status-Register
instructions). Any low to high transition on CE#, before
receiving the last bit of an instruction bus cycle, will termi-
nate the instruction in progress and return the device to
standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.
Description
Read Memory
Read Memory with Dual Address Input and
Data Output
Read Memory with Dual Output
Read Memory at Higher Speed
Erase 4 KByte of
memory array
Erase 32KByte block
of memory array
Erase 64 KByte block
of memory array
Erase Full Memory Array
To Program 1 to 256 Data Bytes
To Program 1 to 256 Data Bytes
Read-Status-Register
Enable-Write-Status-Register
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID Read
Enable HOLD# pin functionality of the RST#/
HOLD# pin
Read Security ID
Program User Security ID area
Lockout Security ID Programming
Op Code Cycle
1
0000 0011b (03H)
1011 1011b (BBH)
0011 1011b (3BH)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H) or
1100 0111b (C7H)
0000 0010b (02H)
1010 0010b (A2H)
0000 0101b (05H)
0101 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
1010 1011b (ABH)
1001 1111b (9FH)
1010 1010b (AAH)
1000 1000b (88H)
1010 0101b (A5H)
1000 0101b (85H)
Address
Cycle(s)
2
3
3
3
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
1
1
0
Dummy
Cycle(s)
0
1
3
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Data
Cycle(s)
1 to
∞
1 to
∞
3
1 to
∞
3
1 to
∞
0
0
0
0
1 to 256
1 to 128
3
1 to
∞
0
1
0
0
1 to
∞
3 to
∞
0
1 to 32
1 to 24
0
T6.0
1392
One bus cycle is eight clock periods.
Address bits above the most significant bit can be either V
IL
or V
IH
.
One bus cycle is four clock periods (dual operation)
4KByte Sector Erase addresses: use A
MS
-A
12,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
9
SST [ SILICON STORAGE TECHNOLOGY, INC ]
