4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
Block Protection (BP3,BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be soft-
ware protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (V
IL
), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (V
IH
), the BPL bit has no
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
TABLE 4: Software Status Register Block Protection
FOR
SST25VF040B
1
Status Register Bit
2
Protection Level
None
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
BP3
X
X
X
X
X
X
X
X
BP2
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protected Memory Address
4 Mbit
None
70000H-7FFFFH
60000H-7FFFFH
40000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
T4.0 1295
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
©2009 Silicon Storage Technology, Inc.
S71295-05-000
10/09
7
SST [ SILICON STORAGE TECHNOLOGY, INC ]
