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SST25VF512-20-4C-SAE 参数 Datasheet PDF下载

SST25VF512-20-4C-SAE图片预览
型号: SST25VF512-20-4C-SAE
PDF下载: 下载PDF文件 查看货源
内容描述: 512 Kbit的SPI串行闪存 [512 Kbit SPI Serial Flash]
分类和应用: 闪存
文件页数/大小: 23 页 / 264 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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512 Kbit SPI Serial Flash  
SST25VF512  
Data Sheet  
Sector-Erase  
The Sector-Erase instruction clears all bits in the selected 4  
KByte sector to FFH. A Sector-Erase instruction applied to  
a protected memory area will be ignored. Prior to any Write  
operation, the Write-Enable (WREN) instruction must be  
executed. CE# must remain active low for the duration of  
the any command sequence. The Sector-Erase instruction  
is initiated by executing an 8-bit command, 20H, followed  
by address bits [A23-A0]. Address bits [AMS-A12]  
(AMS = Most Significant address) are used to determine the  
sector address (SAX), remaining address bits can be VIL or  
VIH. CE# must be driven high before the instruction is exe-  
cuted. The user may poll the Busy bit in the software status  
register or wait TSE for the completion of the internal self-  
timed Sector-Erase cycle. See Figure 7 for the Sector-  
Erase sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
24  
MODE 0  
SCK  
20  
ADD.  
MSB  
ADD.  
ADD.  
SI  
MSB  
HIGH IMPEDANCE  
SO  
1192 F06.12  
FIGURE 7: SECTOR-ERASE SEQUENCE  
Block-Erase  
The Block-Erase instruction clears all bits in the selected 32  
KByte block to FFH. A Block-Erase instruction applied to a  
protected memory area will be ignored. Prior to any Write  
operation, the Write-Enable (WREN) instruction must be  
executed. CE# must remain active low for the duration of  
any command sequence. The Block-Erase instruction is  
initiated by executing an 8-bit command, 52H, followed by  
address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most  
significant address) are used to determine block address  
(BAX), remaining address bits can be VIL or VIH. CE# must  
be driven high before the instruction is executed. The user  
may poll the Busy bit in the software status register or wait  
TBE for the completion of the internal self-timed Block-  
Erase cycle. See Figure 8 for the Block-Erase sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
24  
MODE 0  
SCK  
52  
ADD.  
MSB  
ADD.  
ADD.  
SI  
MSB  
HIGH IMPEDANCE  
SO  
1192 F28.11  
FIGURE 8: BLOCK-ERASE SEQUENCE  
©2004 Silicon Storage Technology, Inc.  
S71192-06-000  
4/04  
10