1 Mbit SPI Serial Flash
SST25VF010
Data Sheet
PRODUCT IDENTIFICATION
DEVICE OPERATION
The SST25VF010 is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
00000H
BFH
SST25VF010
00001H
49H
The SST25VF010 supports both Mode 0 (0,0) and Mode 3
(1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
T2.0 1233
MEMORY ORGANIZATION
The SST25VF010 SuperFlash memory array is organized
in 4 KByte sectors with 32 KByte overlay blocks.
©2003 Silicon Storage Technology, Inc.
S71233-01-000
8/03
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
