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SST25VF010-20-4C-SA 参数 Datasheet PDF下载

SST25VF010-20-4C-SA图片预览
型号: SST25VF010-20-4C-SA
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位的SPI串行闪存 [1 Mbit SPI Serial Flash]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 22 页 / 281 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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1 Mbit SPI Serial Flash  
SST25VF010  
Data Sheet  
Write-Status-Register (WRSR)  
When WP# is high, the lock-down function of the BPL bit is  
disabled and the BPL, BP0, and BP1 bits in the status reg-  
ister can all be changed. As long as BPL bit is set to 0 or  
WP# pin is driven high (VIH) prior to the low-to-high transi-  
tion of the CE# pin at the end of the WRSR instruction, the  
BP0, BP1, and BPL bit in the status register can all be  
altered by the WRSR instruction. In this case, a single  
WRSR instruction can set the BPL bit to “1” to lock down  
the status register as well as altering the BP0 and BP1 bit  
at the same time. See Table 3 for a summary description of  
WP# and BPL functions. CE# must be driven low before  
the command sequence of the WRSR instruction is  
entered and driven high before the WRSR instruction is  
executed. See Figure 13 for EWSR and WRSR instruction  
sequences.  
The Write-Status-Register instruction works in conjunction  
with the Enable-Write-Status-Register (EWSR) instruction  
to write new values to the BP1, BP0, and BPL bits of the  
status register. The Write-Status-Register instruction must  
be executed immediately after the execution of the Enable-  
Write-Status-Register instruction (very next instruction bus  
cycle). This two-step instruction sequence of the EWSR  
instruction followed by the WRSR instruction works like  
SDP (software data protection) command structure which  
prevents any accidental alteration of the status register val-  
ues. The Write-Status-Register instruction will be ignored  
when WP# is low and BPL bit is set to “1”. When the WP#  
is low, the BPL bit can only be set from “0” to “1” to lock-  
down the status register, but cannot be reset from “1” to “0”.  
CE#  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15  
MODE 3  
MODE 0  
MODE 3  
MODE 0  
SCK  
STATUS  
REGISTER IN  
50  
01  
7 6 5 4 3 2 1 0  
MSB  
SI  
MSB  
MSB  
HIGH IMPEDANCE  
SO  
1233 F13.1  
FIGURE 13: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE  
©2003 Silicon Storage Technology, Inc.  
S71233-01-000  
8/03  
13