8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
Block Protection (BP3,BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be soft-
ware protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (VIH), the BPL bit has no
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
TABLE 4: Software Status Register Block Protection for SST25VF080B1
Status Register Bit2
Protected Memory Address
8 Mbit
Protection Level
None
BP3
X
BP2
0
BP1
0
BP0
0
None
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
X
0
0
1
F0000H-FFFFFH
E0000H-FFFFFH
C0000H-FFFFFH
80000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
X
1
1
1
T4.0 1296
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
7
SST [ SILICON STORAGE TECHNOLOGY, INC ]
