512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
MEMORY ORGANIZATION
The SST25WF512/010/020/040 SuperFlash memory
arrays are organized in uniform 4 KByte with 16 KByte, 32
KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay eras-
able blocks.
(CE#) is used to select the device, and data is accessed
through the Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK).
The SST25WF512/010/020/040 support both Mode 0
(0,0) and Mode 3 (1,1) of SPI bus operations. The differ-
ence between the two modes, as shown in Figure 3, is the
state of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25WF512/010/020/040 are accessed through
the SPI (Serial Peripheral Interface) bus compatible proto-
col. The SPI bus consist of four control lines; Chip Enable
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1328 F03.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
