64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
MEMORY ORGANIZATION
The SST25VF064C SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF064C supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF064C is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consists of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1392 F04.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
