32 Mbit SPI Serial Flash
SST25VF032B
Data Sheet
PIN DESCRIPTION
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
HOLD#
SCK
SI
HOLD#
SCK
SI
Top View
Top View
WP#
WP#
V
SS
V
SS
1327 8-WSON P1.0
1327 8-SOIC P1.0
Notes: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-
Write Detection” on page 11 for details.
FIGURE 2: Pin Assignments for 8-Lead SOIC
TABLE 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
RY/BY#
CE#
Ready / Busy pin
Chip Enable
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
Hold
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD
VSS
Power Supply
Ground
To provide power supply voltage: 2.7-3.6V
T1.0 1327
©2009 Silicon Storage Technology, Inc.
S71327-03-000
05/09
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
