2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST25VF020
SST25VF040
00001H
00001H
43H
44H
T2.0 1231
DEVICE OPERATION
The SST25VF020/040 is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF020/040 supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state
of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
Data
BFH
00000H
MEMORY ORGANIZATION
The SST25VF020/040 SuperFlash memory array is orga-
nized in 4 KByte sectors with 32 KByte overlay blocks.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1231 F02.1
HIGH IMPEDANCE
FIGURE 2: SPI P
ROTOCOL
©2004 Silicon Storage Technology, Inc.
S71231-04-000
6/04
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
