512 Kbit SPI Serial Flash
SST25VF512A
Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 4 describes the function of each bit in the software
status register.
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Bit
Name Function
Power-up
Read/Write
0
BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
BP0
BP1
RES
AAI
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Reserved for future use
1
1
0
0
R/W
R/W
N/A
R
4:5
6
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
T4.0 1264
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indi-
cates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming
reached its highest memory address
•
•
•
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
©2006 Silicon Storage Technology, Inc.
S71264-02-000
1/06
6
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