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SST25VF040B 参数 Datasheet PDF下载

SST25VF040B图片预览
型号: SST25VF040B
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位的SPI串行闪存 [4 Mbit SPI Serial Flash]
分类和应用: 闪存
文件页数/大小: 28 页 / 351 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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4 Mbit SPI Serial Flash  
SST25VF040B  
Data Sheet  
High-Speed-Read (50 MHz)  
The High-Speed-Read instruction supporting up to 50 MHz  
Read is initiated by executing an 8-bit command, 0BH, fol-  
lowed by address bits [A23-A0] and a dummy byte. CE#  
must remain active low for the duration of the High-Speed-  
Read cycle. See Figure 5 for the High-Speed-Read  
sequence.  
addresses until terminated by a low to high transition on  
CE#. The internal address pointer will automatically incre-  
ment until the highest memory address is reached. Once  
the highest memory address is reached, the address  
pointer will automatically increment to the beginning (wrap-  
around) of the address space. Once the data from address  
location 7FFFFH has been read, the next output will be  
from address location 00000H.  
Following a dummy cycle, the High-Speed-Read instruc-  
tion outputs the data starting from the specified address  
location. The data output stream is continuous through all  
CE#  
MODE 3  
MODE 0  
0
1
2
3
4
5
6
7
8
15 16  
23 24  
31 32  
39 40  
47 48  
55 56  
63 64  
80  
71 72  
SCK  
0B  
ADD.  
ADD.  
ADD.  
X
SI  
MSB  
MSB  
N
OUT  
N+1  
N+2  
N+3  
D
OUT  
N+4  
HIGH IMPEDANCE  
D
OUT  
D
D
D
OUT  
SO  
OUT  
MSB  
1295 HSRdSeq.0  
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V or V  
)
IH  
IL  
FIGURE 5: HIGH-SPEED-READ SEQUENCE  
©2006 Silicon Storage Technology, Inc.  
S71295-01-000  
1/06  
10