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SST25LF040A-33-4E-QAE 参数 Datasheet PDF下载

SST25LF040A-33-4E-QAE图片预览
型号: SST25LF040A-33-4E-QAE
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位/ 4兆位的SPI串行闪存 [2 Mbit / 4 Mbit SPI Serial Flash]
分类和应用: 闪存
文件页数/大小: 26 页 / 301 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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2 Mbit / 4 Mbit SPI Serial Flash  
SST25LF020A / SST25LF040A  
Data Sheet  
Read (20 MHz)  
The Read instruction supports up to 20 MHz, it outputs the  
data starting from the specified address location. The data  
output stream is continuous through all addresses until ter-  
minated by a low to high transition on CE#. The internal  
address pointer will automatically increment until the high-  
est memory address is reached. Once the highest memory  
address is reached, the address pointer will automatically  
increment to the beginning (wrap-around) of the address  
space, i.e. for 4 Mbit density, once the data from address  
location 7FFFFH had been read, the next output will be  
from address location 00000H.  
The Read instruction is initiated by executing an 8-bit com-  
mand, 03H, followed by address bits [A23-A0]. CE# must  
remain active low for the duration of the Read cycle. See  
Figure 4 for the Read sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
39  
40  
47 48  
55 56  
63 64  
70  
24  
32  
MODE 0  
SCK  
03  
ADD.  
MSB  
HIGH IMPEDANCE  
ADD.  
ADD.  
SI  
MSB  
N
OUT  
N+1  
N+2  
N+3  
N+4  
D
OUT  
D
D
D
D
OUT  
OUT  
OUT  
SO  
MSB  
1242 F04.0  
FIGURE 4: READ SEQUENCE  
©2006 Silicon Storage Technology, Inc.  
S71242-05-000  
1/06  
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