2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Data Sheet
PIN DESCRIPTION
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
HOLD#
SCK
SI
HOLD#
SCK
SI
Top View
Top View
WP#
WP#
V
SS
V
SS
1242 08-wson P2.0
1242 08-soic P1.0
8-LEAD SOIC
8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name
Functions
To provide the timing of the serial interface.
SCK
Serial Clock
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI
Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
WP#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
Power Supply To provide power supply (3.0-3.6V).
Ground
HOLD# Hold
VDD
VSS
T1.0 1242
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
