2.4-2.5 GHz Power Amplifier
SST12LP00
Preliminary Specifications
FUNCTIONAL BLOCKS
Bias/Gain Control
RFOUT/VCC2
GCTL
PDC
VCC1
VCCb
RFIN
1283 B1.1
FIGURE 1: Functional Block Diagram
PIN ASSIGNMENTS
Top View
(contacts facing down)
RFOUT/VCC2
6
GCTL
PDC
1
2
VCC1
VCCb
5
4
RF and DC GND
0
3
RFIN
1283 6-vqfn-uqfn P1.1
FIGURE 2: Pin Assignments for 6-contact VQFN and UQFN
PIN DESCRIPTIONS
TABLE 1: Pin Description
Symbol
Pin No. Pin Name
Type1 Function
The center pad should be connected to RF ground with several low
GND
0
Ground
inductance, low resistance vias.
Power Amplifier Gain Control
Power-down Control
GCTL
1
2
3
4
5
6
PDC
RFIN
I
RF input, DC decoupled
VCCb
Power Supply
Power Supply
PWR
PWR
Vcc power supply, bias circuit
Vcc power supply, 1st stage
VCC1
RFOUT/VCC2
O/PWR Vcc power supply, 2nd stage
T1.1 1283
1. I=Input, O=Output
©2006 SST Communications Corp.
S71283-01-000
3/06
2
SST [ SILICON STORAGE TECHNOLOGY, INC ]
