M25PE10, M25PE20
device from inadvertent Write, Program or Erase
instructions.
pulses that is a multiple of eight, before they
are accepted for execution.
Status Register
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
–
–
–
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction comple-
tion
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
–
–
–
–
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Table 2. Status Register Format
b7
0
b0
0
0
0
0
0
WEL WIP
■
The Hardware Protected mode is entered
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertent
Write, Program and Erase instructions while
the device is not in active use.
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25PE10 and
M25PE20 feature the following data protection
mechanisms:
■
■
■
Power On Reset and an internal timer (t
)
PUW
can provide protection against inadvertent
changes while the power supply is outside the
operating specification.
■
Program, Erase and Write instructions are
checked that they consist of a number of clock
8/37
SST [ SILICON STORAGE TECHNOLOGY, INC ]
