FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
11.0 INTERRUPTS
11.1 Interrupt Priority and Polling Sequence
The device supports eight interrupt sources under a four level priority scheme. Table 11-1 summarizes the polling
sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt
vector. (See Figure 11-1)
TABLE 11-1: INTERRUPT POLLING SEQUENCE
Vector
Address
Interrupt
Enable
Interrupt
Priority
Service
Priority
Wake-Up
Power-down
Description
Ext. Int0
Brown-out
T0
Interrupt Flag
IE0
-
0003H
004BH
000BH
0013H
001BH
0033H
003BH
0043H
0023H
002BH
EX0
EBO
ET0
EX1
ET1
EC
PX0/H
PBO/H
PT0/H
PX1/H
PT1/H
PPCH
PX2/H
PX3/H
PS/H
1(highest)
yes
no
no
yes
no
no
no
no
no
2
3
TF0
Ext. Int1
T1
IE1
4
TF1
5
PCA
CF/CCFn
IE2
6
Ext. Int. 2
Ext. Int. 3
UART/SPI
T2
EX2
EX3
ES
7
IE3
8
TI/RI/SPIF
TF2, EXF2
9
ET2
PT2/H
10
no
T11-1.0 1255
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
64
SST [ SILICON STORAGE TECHNOLOGY, INC ]
