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39VF040 参数 Datasheet PDF下载

39VF040图片预览
型号: 39VF040
PDF下载: 下载PDF文件 查看货源
内容描述: 512千位/ 1兆位/ 2兆位/ 4兆位( X8 )多用途闪存 [512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash]
分类和应用: 闪存
文件页数/大小: 24 页 / 283 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash  
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040  
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040  
Data Sheet  
Data# Polling (DQ7)  
Software Data Protection (SDP)  
When the SST39LF512/010/020/040 and SST39VF512/  
010/020/040 are in the internal Program operation, any  
attempt to read DQ7 will produce the complement of the  
true data. Once the Program operation is completed, DQ7  
will produce true data. The device is then ready for the next  
operation. During internal Erase operation, any attempt to  
read DQ7 will produce a 0. Once the internal Erase opera-  
tion is completed, DQ7 will produce a 1. The Data# Polling  
is valid after the rising edge of fourth WE# (or CE#) pulse  
for Program operation. For Sector- or Chip-Erase, the  
Data# Polling is valid after the rising edge of sixth WE# (or  
CE#) pulse. See Figure 7 for Data# Polling timing diagram  
and Figure 16 for a flowchart.  
The SST39LF512/010/020/040 and SST39VF512/010/  
020/040 provide the JEDEC approved Software Data Pro-  
tection scheme for all data alteration operation, i.e., Pro-  
gram and Erase. Any Program operation requires the  
inclusion of a series of three byte sequence. The three  
byte-load sequence is used to initiate the Program opera-  
tion, providing optimal protection from inadvertent Write  
operations, e.g., during the system power-up or power-  
down. Any Erase operation requires the inclusion of six  
byte load sequence. These devices are shipped with the  
Software Data Protection permanently enabled. See Table  
4 for the specific software command codes. During SDP  
command sequence, invalid commands will abort the  
device to read mode, within TRC  
.
Toggle Bit (DQ6)  
Product Identification  
During the internal Program or Erase operation, any con-  
secutive attempts to read DQ6 will produce alternating 0s  
and 1s, i.e., toggling between 0 and 1. When the internal  
Program or Erase operation is completed, the toggling will  
stop. The device is then ready for the next operation. The  
Toggle Bit is valid after the rising edge of fourth WE# (or  
CE#) pulse for Program operation. For Sector- or Chip-  
Erase, the Toggle Bit is valid after the rising edge of sixth  
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-  
gram and Figure 16 for a flowchart.  
The Product Identification mode identifies the devices as  
the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020  
and SST39LF/VF040 and manufacturer as SST. This  
mode may be accessed by software operations. Users  
may use the Software Product Identification operation to  
identify the part (i.e., using the device ID) when using multi-  
ple manufacturers in the same socket. For details, see  
Table 4 for software operation, Figure 11 for the Software  
ID Entry and Read timing diagram, and Figure 17 for the  
Software ID entry command sequence flowchart.  
Data Protection  
TABLE 1: PRODUCT IDENTIFICATION  
The SST39LF512/010/020/040 and SST39VF512/010/  
020/040 provide both hardware and software features to  
protect nonvolatile data from inadvertent writes.  
Address  
Data  
Manufacturers ID  
Device ID  
0000H  
BFH  
Hardware Data Protection  
SST39LF/VF512  
SST39LF/VF010  
SST39LF/VF020  
SST39LF/VF040  
0001H  
0001H  
0001H  
0001H  
D4H  
D5H  
D6H  
D7H  
Noise/Glitch Protection: A WE# or CE# pulse of less than 5  
ns will not initiate a Write cycle.  
VDD Power Up/Down Detection: The Write operation is  
inhibited when VDD is less than 1.5V.  
T1.1 395  
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#  
high will inhibit the Write operation. This prevents inadvert-  
ent writes during power-up or power-down.  
Product Identification Mode Exit/Reset  
In order to return to the standard Read mode, the Software  
Product Identification mode must be exited. Exit is accom-  
plished by issuing the Software ID Exit command  
sequence, which returns the device to the Read operation.  
Please note that the Software ID Exit command is ignored  
during an internal Program or Erase operation. See Table 4  
for software command codes, Figure 12 for timing wave-  
form, and Figure 17 for a flowchart.  
©2001 Silicon Storage Technology, Inc.  
S71150-03-000 6/01 395  
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