512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
395 ILL F05.0
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
for SST39LF/VF020 and A for SST39LF/VF040
A
18
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
D
D#
D#
D
395 ILL F06.0
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
for SST39LF/VF020 and A for SST39LF/VF040
A
18
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01 395
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
