512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW0
SW5
334 ILL F17.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020 and A for SST39LF/VF040
15 16 17 18
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence for
Software ID Entry
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
7-0
AA
55
90
BF
Device ID
SW0
SW1
SW2
395 ILL F09.2
Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
FIGURE 11: SOFTWARE ID ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01 395
13
SST [ SILICON STORAGE TECHNOLOGY, INC ]
