W320-04
Function Table[1]
66BUFF[0:2]/
3V66[2:4]
(MHz)
CPU
(MHz)
3V66[0:1]
(MHz)
66IN/3V66_5 PCI_F/PCI
(MHz) (MHz)
USB/DOT
S2 S1 S0
REF0(MHz)
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
(MHz)
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66 MHz
66 MHz
66IN
66 MHz Input 66IN/2
66 MHz Input 66IN/2
66 MHz Input 66IN/2
66 MHz Input 66IN/2
1
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
66IN
1
66IN
1
66IN
0
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
0
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
0
0
Mid
Mid
Mid
Mid
Hi-Z
Hi-Z
TCLK/2
TCLK/4
TCLK/4
TCLK/4
Reserved
Reserved
TCLK/8
Reserved
Reserved
TCLK
TCLK/2
Reserved
Reserved
5, 6, 7
–
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved
Reserved
–
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF = VDD/(3*Rr)
Rr = 221 1%, IREF = 5.00 mA
Rr = 475 1%, IREF = 2.32 mA
Output Current VOH @ Z
0
1
50:
50:
I
OH = 4*IREF 1.0V @ 50
OH = 6*IREF 0.7V @ 50
I
Clock Driver Impedances
Impedance
Buffer Name
CPU, CPU#
V
DD Range
Buffer Type
Min. :
Typ. :
50
Max. :
Type X1
Type 5
REF
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
12
12
12
12
30
55
55
60
60
PCI, 3V66, 66BUFF
Type 5
30
USB
DOT
Type 3A
Type 3B
30
30
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP#
CPU
CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
IREF*2 FLOAT LOW
LOW
ON
LOW LOW
LOW
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
FLOAT
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
Note:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation
3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6. Required for DC output impedance verification.
7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Rev 1.0,November 25, 2006
Page 3 of 16