W144
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100.2 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
ꢀ
f
14.31818
tR
1
1
–
–
–
–
4
4
tF
Measured from 2.0V to 0.4V
tD
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
45
–
55
1.5
fST
Frequency Stabilization
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
–
15
–
:
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
14.318
–
Max. Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
MHz
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
0.5
45
–
2
2
V/ns
V/ns
ꢀ
–
tF
Output Fall Edge Rate
Duty Cycle
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
–
–
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
ms
from Power-up (cold
start)
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
–
40
–
:
48 MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
MHz
ppm
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
–48.008–
fD
Deviation from 48 MHz (48.008 – 48)/48
+167
p/q
tR
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
–57/17
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
–
–
–
–
–
2
2
V/ns
V/ns
ꢀ
tF
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
55
3
fST
FrequencyStabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
ms
from Power-up (cold
start)
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
–
40
–
:
24 MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
24.004
+167
57/34
–
Max.
Unit
MHz
ppm
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
fD
Deviation from 24 MHz (24.004 – 24)/24
p/q
tR
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
2
2
V/ns
V/ns
ꢀ
tF
–
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
–
55
Rev 1.0,November 21, 2006
Page 12 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
