W144
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
CPU = 100.2 MHz
Parameter
tP
tH
Description
Period
Test Condition/Comments
Min.
Typ. Max. Min. Typ. Max. Unit
Measured on rising edge at 1.5V
30
–
–
–
–
30
–
–
–
–
ns
ns
High Time
Duration of clock cycle above 2.4V, 5.6
at min. edge rate (1.5V/ns)
3.3
tL
Low Time
Duration of clock cycle below 0.4V,
at min. edge rate (1.5V/ns
5.3
–
–
–
4
3.1
1.5
–
–
–
4
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1.5
V/ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
1.5
1
–
–
–
–
4
5
1.5
1
–
–
–
–
4
5
V/ns
ns
tPLH
tPHL
tD
Prop Delay LH
Prop Delay HL
Duty Cycle
Input edge rate faster than 1V/ns
Input edge rate faster than 1 V/ns
1
5
1
5
ns
Measured on rising and falling edge
at 1.5V,at min. edge rate (1.5 V/ns)
45
55
45
55
ꢀ
tJC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
–
–
250
–
–
250
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
–
–
–
250
4
–
–
–
250
4
ps
ns
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs.
Measured on rising edge at 1.5V.
CPU leads PCI output.
1.5
1.5
fST
Frequency
Stabilization from
Power-up (cold start) Short cycles exist prior to frequency
stabilization.
Assumes full supply voltage
reachedwithin1msfrompower-up.
–
–
–
3
–
–
–
–
3
–
ms
Zo
AC Output
Impedance
Average value during switching
transition. Used for determining
series termination value.
30
30
:
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100.2 MHz
Parameter
tP
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min.
29.9
12.0
12.0
1
Typ.
–
Max.
Unit
ns
Period
–
–
tH
tL
High Time
–
ns
Low Time
–
–
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
–
4
V/ns
V/ns
ꢀ
Measured from 2.4V to 0.4V
1
–
4
tD
tJC
Measured on rising and falling edge at 1.5V
45
–
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
–
–
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
–
–
–
500
4.0
ps
ns
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
fST
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Assumes full supply voltage reached within
–
–
–
3.0
–
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
30
:
Rev 1.0,November 21, 2006
Page 11 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
