SL23EP08
Switching Electrical Characteristics (I-Grade-Cont.)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
CL=15pF, Fout=66 MHz, all versions
Output Duty Cycle
DC3
DC4
DC5
tr/f1
45
45
40
-
50
50
50
-
55
55
%
%
Measured at VDD/2
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
Output Duty Cycle
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Duty Cycle
60
%
CL=30pF, -1, -2 and -4 versions
Measured at 0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
2.2
1.8
1.5
1.2
220
220
220
ns
ns
ns
ns
ps
ps
ps
CL=15pF, -1, -2 and -4 versions
Measured at 0.6 to 1.8V
tr/f2
-
-
CL=30pF, -1H and -2H and versions
Measured at 0.6 to 1.8V
tr/f3
-
-
CL=15pF, -1H and -2H and versions
Measured at 0.6 to 1.8V
tr/f4
-
-
Output-to-Output Skew
on Same Bank
-1 and -2, measured from 0.8V to
2.0V, and outputs are equally loaded
SKW2
SKW2
SKW3
-
100
100
100
Output-to-Output Skew
on Same Bank
-1H and -2H and -4, measured at
VDD/2 and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1, -1H, 2H and -4, measured at
VDD/2 and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-2, measured at VDD/2 and outputs
are equally loaded
SKW4
SKW5
-
-
180
275
375
550
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded and S2=S1=1
Dt
-200
-
200
ps
Fout=66 MHz and CL=15pF
Fout=133MHz and CL=15pF
Fout=66 MHz and CL=15pF
Fout=166MHz and CL=15pF
From 0.95VDD and valid CLKIN
-
-
-
-
-
80
70
70
60
-
175
150
150
125
1.0
ps
ps
ps
ps
ms
Cycle-to-Cycle Jitter
CCJ1
(-1, -2 and -4 Versions)
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
PLL Lock Time
tLOCK
Rev 1.4, May 28, 2007
Page 14 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
