SL23EP04NZ
General Description
Output Clock Skew
The SL23EP04NZ is a low skew, jitter and power fanout
clock distribution buffer designed to produce up to four
(4) clock outputs from one (1) reference input clock, for
high speed clock distribution, including PCI/PCI-X
applications.
All outputs should drive the similar load to achieve output-
to-output skew and input-to-output delay specifications as
given in the switching electrical tables.
Power Supply Range (VDD)
Input and output Frequency Range
The SL23EP04 is designed to operate from 3.3V+/-10% to
2.5V+/-10% VDD power supply range. An internal on-chip
voltage regulator is used to provide to constant power
supply of 1.8V in the core, leading to a consistent and
stable electrical performance in terms of skew and jitter.
The SL23EP04NZ I/O is powered by using VDD.
The input and output frequency is the same (1x) for
SL23EP04NZ-1 and SL23EP04NZ-1Z. The products
operate from DC to 220MHz clock range with up to
30pF output loads at each output.
Contact SLI for 1.8V power supply Fan-Out Buffer and
ZDB products.
OE (Output Enable) Function
The only difference between SL23EP04-1 and
SL23EP04NZ-1Z is the OE logic implementation. When
OE=0, SL23EP04NZ-1 outputs are disabled and outputs
are at Logic Low. In the case of SL23EP04NZ-1Z the
outputs are at High-Z. Refer to the Available OE Logic
Configuration Table. 1 below.
SL2304NZ-1
SL2304NZ-1Z
CLKOUT [1:4]
CLKIN (Pin-1)
OE (Pin-2)
CLKOUT [1:4]
Low
High
Low
High
Low
Low
High
High
Low
Low
Low
High
High-Z
High-Z
Low
High
Table 1. Available SL23EP04 CLKIN and OE Logic Configurations
Rev 1.1, April 16, 2007
Page 3 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
