SL2305
Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol Description
Condition
Min
Max
Unit
MHz
FMAX1
Maximum Frequency [1]
High drive (-1H). All outputs CL=15pF
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
Standard drive, (-1), All outputs CL=30pf
10
140
(Input=Output )
10
10
10
100
100
66
MHz
MHz
MHz
All Active PLL Modes
Input Duty Cycle
Measured at 1.4V, Fout=66MHz,
CL=15pF
INDC
30
40
70
60
%
%
OUTDC
Output Duty Cycle[2]
Measured at 14V, Fout=66MHz,
CL=15pF
tr/f
Rise, Fall Time (3.3V) [2]
(Measured at: 0.8 to 2.0V)
High drive (-1H), CL=10pF
High drive (-1H), CL=30pF
Standard drive (-1), CL=10pF
Standard drive (-1), CL=30pF
–
–
–
–
1.5
1.8
2.2
2.5
ns
ns
ns
ns
t1
t2
t3
Output-to-Output Skew[2]
(Measured at VDD/2)
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
–
120
400
ps
ps
Device-to-Device Skew[2]
(Measured at VDD/2)
All outputs CL=0 or equally loaded, -1 or
-1H drives
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge[2]
Measured at VDD/2
–150
–
150
1.0
ps
tPLOCK
CCJ
PLL Lock Time[2]
Time from 90% of VDD to valid clocks on
all the output clocks
ms
Cycle-to-cycle Jitter [2]
Fin=Fout=66 MHz, <CL=15pF, -1H drive
Fin=Fout=66 MHz, <CL=15pF, -1 drive
Fin=Fout=66 MHz, <CL=30pF, -1H drive
Fin=Fout=66 MHz, <CL=30pF, -1 drive
–
–
–
–
90
ps
ps
ps
ps
100
120
140
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev 1.4, May 25, 2007
Page 6 of 11