W320-04
PWRDWN# Deassertion
10-30 Ps min.
100-200 Ps max.
< 3 ms
66BUFF1/GMCH
66BUFF0,2
PCI
PCI_F (APIC)
PWR_DWN#
CPU
CPU#
3V66
66IN
USB
REF
Note: PCI_STOP# asserted LOW
PWRGD# Timing Diagrams
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
Possible glitch while Clock VCC is coming
up. Will be gone in 0.2–0.3 mS delay.
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
0.2 -- 0.3 ms Wait for
Sample
delay
PWRGD#
VCC W320 CLOCK
GEN
BSELS
State 1 State 2
State 3
State 0
CLOCK STATE
OFF
OFF
ON
CLOCK VCO
ON
CLOCK OUTPUTS
Figure 2. CPU Power Before Clock Power
Rev 1.0,November 25, 2006
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