CY2SSTV16859
13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant
The CY2SSTV16859 operates from a differential clock (CLK
and CLK#) of frequency up to 280 MHz. Data are registered at
crossing of CLK going high and CLK# going low.
Features
• Differential clock inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET# pin
When RESET# is low, the differential input receivers are
disabled, and undriven (floating) data and clock inputs are
allowed. The LVCMOS RESET# input must always be held at
a valid logic high or low level.
• Output drivers have controlled edge rates, so no
external resistors are required.
• Two KV ESD protection
To ensure defined outputs from the register before a stable
clock has been supplied, RESET# must be held in the low
state during power up.
• Latch-up performance exceeds 100 mA per JESD78,
Class II
• 64-pin TSSOP/JEDEC and 56-pin QFN package avail-
ability
In the DDR DIMM application, RESET# is completely
asynchronous with respect to CLK# and CLK. Therefore, no
timing relationship can be guaranteed between the two. When
entering reset, the register is cleared and the outputs are
driven low quickly, relative to the time to disable the differential
input receivers, thus ensuring no glitches on the output.
However, when coming out of reset, the register becomes
active quickly, relative to the time to enable the differential
input receivers.
• JEDEC specification supported
Description
This 13-bit to 26-bit registered buffer is designed for 2.3V to
2.7 VDD operations.
All inputs are compatible with the JEDEC Standard for SSTL-2,
except the LVCMOS reset (RESET#) input. All outputs are
SSTL_2, Class II compatible.
Pin Configuration
Block Diagram
Q13A
Q12A
Q11A
Q10A
Q9A
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
2
3
4
D12
VDD
VDDQ
GND
D11
5
VDDQ
GND
Q8A
6
7
8
RESET #
Q7A
D10
9
CLK
CLK #
Q6A
D9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Q5A
GND
D8
Q4A
Q3A
D7
D1
Q2A
RESET #
GND
CLK #
CLK
VDDQ
VDD
VREF
D6
Q1A
Q1B
D
C
GND
Q1A
VREF
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
R
To 12 Other Channels
GND
D5
Q8B
Q7B
D4
Q6B
D3
GND
VDDQ
Q5B
GND
VDDQ
VDD
D2
Q4B
Q3B
D1
Q2B
GND
VDDQ
Q1B
Rev 1.0, November 21, 2006
Page 1 of 7
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