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CY2SSTV16857ZXIT 参数 Datasheet PDF下载

CY2SSTV16857ZXIT图片预览
型号: CY2SSTV16857ZXIT
PDF下载: 下载PDF文件 查看货源
内容描述: 14位Regstered缓冲PC2700- / PC3200兼容 [14-Bit Regstered Buffer PC2700-/PC3200-Compliant]
分类和应用: 触发器逻辑集成电路电视光电二极管PC
文件页数/大小: 7 页 / 91 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2SSTV16857  
Slew Rate  
LVCMOS  
RESET  
Input  
VDD  
VDD/2  
0 V  
The following table describes output-buffer slew-rate charac-  
teristics that are sufficient to meet the requirements of regis-  
tered DDR DIMM performance and timings. These character-  
istics are not necessarily production tested but can be  
guaranteed by design or characterization. Compliance with  
these rates is not mandatory if it can be adequately demon-  
strated that alternate characteristics meet the requirements of  
the registered DDR DIMM application. This information does  
not necessarily have to appear in the device data sheet.  
VDD/2  
tinact  
10ꢀ  
tact  
IDD  
IDDH  
90ꢀ  
IDDL  
Obtain rise and fall time measurements by using the same  
procedure for obtaining “Ramp” data according to the current  
WIA IBIS specification. In particular it is very important to note  
that the following slew rates are specified at the output of the  
die, without package parasitics in the power, ground or output  
paths. The measurement points are at 20ꢀ and 80ꢀ. The  
slew-rate test load shall be a 50-ohm resistor to GND for Rise  
and a 50-ohm resistor to VDDQ for fall. The dV/dt ratio is  
reduced to V/ns.  
Figure 2. Voltage Waveforms Enable and Disable Times  
Low- and High-level Enabling[11]  
VI(PP)  
VICR  
VICR  
Input  
tPLH  
tPHL  
VOH  
VOL  
Table 5. Output Buffer Slew-Rate Characteristics  
VTT  
VTT  
dV/dt  
Rise  
Fall  
Min.  
Max.  
4 V/ns  
4 V/ns  
Output  
0.85 V/ns  
1.00 V/ns  
Figure 3. Voltage Waveforms Propagation Delay Times[12]  
Test Configurations[9, 10]  
VDD = 2.5V 0.2V  
LVCMOS  
VIH  
RESET  
Input  
VDD/2  
VIL  
Timing Diagrams  
tPHL  
VTT  
VI(PP)  
VICR  
th  
VOH  
VOL  
Output  
Timing Input  
tsu  
Figure 4. Voltage Waveforms Propagation Delay Times[11  
V T T  
VIH**  
VIL***  
VREF*  
Data Input  
VREF*  
R L = 5 0 O h m  
F ro m  
O u tp u t  
T e s t P o in t  
Figure 1. Voltage Waveforms Set-up and Hold  
Times[11, 13, 14]  
U n d e r  
T e s t  
C L = 3 0 p F  
Figure 5. Load Circuit[8]  
tw  
VIH**  
Input  
VREF*  
VREF*  
VIL***  
Figure 6. Voltage Waveforms Pulse Duration[13, 14]  
Notes:  
8. CL includes probe and jig capacitance.  
9. IDD tested with clock and data inputs held at VDD or VSS, and IO = 0 mA.  
10. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50 ohm input slew rate = 1 V/ns 20ꢀ (unless otherwise  
specified).  
11. the outputs are measured one at a time with one transition per measurement.  
12. *VTT = VREF = VDDQ/2.  
13. **VIH = VREF + 350 mV (AC voltage levels).  
14. ***VIL = VREF – 350 mV (AC voltage levels).  
Rev 1.0,November 21, 2006  
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