CY28442-2
Clock Generator for Intel£ꢀAlviso Chipset
• 96 /100 MHz Spreadable differential clock.
• 33 MHz PCI clock
Features
• Compliant to Intel£ CK410M
• Supports Intel Pentium-M CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• Low-voltage frequency select input
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin TSSOP package
CPU
SRC
x5/6
PCI
x 6
REF
x 2
DOT96
x 2
USB_48
x 1
• SRC clocks independently stoppable through
CLKREQ#[A:B]
x2 / x3
Block Diagram
Pin Configuration
VDD_REF
XIN
14.318MHz
Crystal
REF
XOUT
PLL Reference
Divider
PCI2/SEL_CLKREQ**
PCI_STP#
CPU_STP#
FS_C(TEST_SEL)/REF0
REF1
VSSA2
XIN
XOUT
VDDA2
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
ITP_EN/PCIF0
IREF
VDD_CPU
CPUT
PCI_STP#
PLL1
CPU
CPUC
CPU_STP#
CLKREQ[A:B]#
FS_[C:A]
VDD_CPU
CPUT_ITP/SRCT7
CPUC_ITP/SRCC7
VDD_SRC
SRCT[1:5]
**96_100_SEL/PCIF1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VTTPWRGD#/PD
VDD_48
SDATA
SCLK
CPUC[1:5]
VDD_PCI
FS_A/48M_0
VSS_48
DOT96T
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
PCI
VDD_PCI
PCIF
DOT96C
VDD_48MHz
96_100_SSCT
96_100_SSCC
FS_B/TESTMODE
96_100_SSCT
96_100_SSCC
PLL2
96MSS
Divider
Divider
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
VSSA
VDDA
VDD_48MHz
DOT96T
DOT96C
PLL3
FIXED
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7
VDD_SRC_ITP
CLKREQA#/SRCT6
CLKREQB#/SRCC6
SRCT5
VDD_48
USB
SRCT3
VTTPWR_GD#/PD
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
SRCC5
VSS_SRC
56 pin TSSOP/SSOP
I2C
Logic
SDATA
SCLK
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 19
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
