CY28439
For Differential CPU, SRC and DOT96 Output
Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
M e a s u re m e n t
P o in t
ꢁ ꢁ :
C P U T
S R C T
D O T 9 6 T
2 p F
ꢆ ꢇ ꢈꢇ :
ꢄ ꢃ ꢃ : ꢀD iffe re n tia l
M e a s u re m e n t
P o in t
2 p F
ꢁ ꢁ :
C P U C
S R C C
D O T 9 6 C
IR E F
ꢆ ꢇ ꢈꢇ :
ꢆ ꢉ ꢊ :
Figure 10. 0.7V Single-ended Load Configuration
3 .3 V s ig n a ls
T D C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0 V
T R
T F
Figure 11. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Lead-free
Package Type
Product Flow
CY28439OXC
CY28439OXCT
CY28439ZXC
CY28439ZXCT
56-pin SSOP
Commercial, 0q to 85qC
Commercial, 0q to 85qC
Commercial, 0q to 85qC
Commercial, 0q to 85qC
56-pin SSOP – Tape and Reel
56-pin TSSOP
56-pin TSSOP – Tape and Reel
Rev 1.0,November 21, 2006
Page 20 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
