CY28437
PD (Power-down) Clarification
output are held with “Diff clock” pin driven high at 2 x Iref, and
“Diff clock#” tri-state. If the control register PD drive mode bit
corresponding to the output of interest is programmed to “1”,
then both the “Diff clock” and the “Diff clock#” are tri-state. Note
the example below shows CPUT = 133 MHz and PD drive
mode = ‘1’ for all differential outputs. This diagram and
description is applicable to valid CPU frequencies 100, 133,
166, 200, 266, 333, and 400 MHz. In the event that PD mode
is desired as the initial power-on state, PD must be asserted
high in less than 10 Ps after asserting Vtt_PwrGd#.
The VTT_PWRGD#/PD pin is a dual-function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a low value and held prior to turning off the VCOs and
the crystal oscillator.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 Ps of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within four clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
Tstable
<1.8ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 5. Power-down Deassertion Timing Waveform
Rev 1.0,November 20, 2006
Page 14 of 22
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