欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY28435ZXC 参数 Datasheet PDF下载

CY28435ZXC图片预览
型号: CY28435ZXC
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 22 页 / 200 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28435ZXC的Datasheet PDF文件第6页浏览型号CY28435ZXC的Datasheet PDF文件第7页浏览型号CY28435ZXC的Datasheet PDF文件第8页浏览型号CY28435ZXC的Datasheet PDF文件第9页浏览型号CY28435ZXC的Datasheet PDF文件第11页浏览型号CY28435ZXC的Datasheet PDF文件第12页浏览型号CY28435ZXC的Datasheet PDF文件第13页浏览型号CY28435ZXC的Datasheet PDF文件第14页  
CY28435  
Byte 14: Control Register 14 (continued)  
Bit  
@Pup  
Name  
Description  
1
1
PCIF  
Free running 33-MHz Output Drive Strength  
0 = 2x, 1 = 1x  
0
0
Recovery_N8  
Watchdog Recovery Bit  
Byte 15: Control Register 15  
Bit  
7
@Pup  
Name  
Description  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
Watchdog Recovery Bit  
0
0
0
0
0
0
0
0
Recovery N7  
Recovery N6  
Recovery N5  
Recovery N4  
Recovery N3  
Recovery N2  
Recovery N1  
Recovery N0  
6
5
4
3
2
1
0
Byte 16: Control Register 16  
Bit  
@Pup  
Name  
Description  
7
1
REF1  
REF1 Output Enable  
0 = Disable, 1 = Enable  
6
5
1
0
USB48_1  
USB48_1 Output Enable  
0 = Disable, 1 = Enable  
SRC_FREQ_SEL  
SRC Frequency selection  
0: SRC frequency is selected via the FSE pin  
1: SRC frequency is initially set to 167 MHz.  
4
3
0
0
RESERVED  
SRC_SATA  
RESERVED, Set = 0  
SATA PLL Spread Spectrum Enable  
0 = Spread off, 1 = Spread on  
2
1
0
0
0
1
Prog_SRC_EN  
Prog_CPU_EN  
Programmable SRC frequency enable  
0 = disabled, 1 = enabled.  
Programmable CPU frequency enable  
0 = disabled, 1 = enabled.  
Watchdog Autorecovery Watchdog Autorecovery Mode  
0 = Disable (Manual), 1= Enable (Auto)  
Crystal Recommendations  
Crystal Loading  
The CY28435 requires a Parallel Resonance Crystal. Substi-  
tuting a series resonance crystal will cause the CY28435 to  
operate at the wrong frequency and violate the ppm specifi-  
cation. For most applications there is a 300-ppm frequency  
shift between series and parallel crystals due to incorrect  
loading.  
Crystal loading plays a critical role in achieving low ppm perfor-  
mance. To realize low ppm performance, the total capacitance  
the crystal will see must be considered to calculate the appro-  
priate capacitive loading (CL).  
Figure 2 shows a typical crystal configuration using the two  
trim capacitors. An important clarification for the following  
discussion is that the trim capacitors are in series with the  
crystal not parallel. It’s a common misconception that load  
capacitors are in parallel with the crystal and should be  
approximately equal to the load capacitance of the crystal.  
This is not true.  
Table 4. Crystal Recommendations  
Frequency  
(Fund)  
Drive  
(max.)  
Shunt Cap Motional  
(max.)  
Tolerance  
(max.)  
Stability  
(max.)  
Aging  
(max.)  
Cut  
Loading Load Cap  
Parallel 20 pF  
(max.)  
14.31818 MHz  
AT  
0.1 mW  
5 pF  
0.016 pF  
35 ppm  
30 ppm  
5 ppm  
Rev 1.0,November 20, 2006  
Page 10 of 22  
 复制成功!