CY28416
AC Electrical Specifications (continued)
Parameter
TR / TF
TCCJ
Description
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Condition
Measured between 0.4V and 2.4V
Measurement at 1.5V
Min.
0.2
–
Max.
2.1
Unit
ns
1000
ps
ENABLE/DISABLE and SETUP
TSTABLE Clock Stabilization from Power-up
TSS
–
10.0
0
1.8
–
ms
ns
ns
Stopclock Set-up Time
Stopclock Hold Time
TSH
–
Table 6. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
pF
PCI Clocks
48M Clock
REF Clock
30
20
30
pF
pF
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
M e a s u re m e n t
P o in t
T P C B
ꢀ ꢀ :
C P U T
ꢁ ꢂ ꢃꢂ :
2 p F
M e a s u re m e n t
P o in t
2 p F
T P C B
ꢁ ꢂ ꢃꢂ :
ꢀ ꢀ :
C P U C
IR E F
ꢁ ꢄ ꢅ :
Figure 7. 0.7V Load Configuration
Output under Test
tDC
Probe
3.3V
2.4V
1.5V
0.4V
Load
Cap
0V
Tr
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Tf
Rev 1.0,November 22, 2006
Page 13 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
