CY28411-1
For Differential CPU, SRC and DOT96 Output Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
M e a s u re m e n t
P o in t
ꢅ ꢅ :
C P U T
S R C T
D O T 9 6 T
2 p F
ꢆ ꢇ ꢈꢇ :
ꢁ ꢄ ꢄ : ꢀD iffe re n tia l
M e a s u re m e n t
P o in t
2 p F
ꢅ ꢅ :
C P U C
S R C C
D O T 9 6 C
IR E F
ꢆ ꢇ ꢈꢇ :
ꢆ ꢉ ꢊ :
Figure 14. 0.7V Single-ended Load Configuration
O utput under Test
tDC
Probe
3.3V
2.4V
1.5V
0.4V
Loas
Cap
0V
Tr
Tf
Figure 15. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Lead-free
Package Type
Product Flow
CY28411OXC-1
CY28411OXC-1T
CY28411ZXC-1
CY28411ZXC-1T
56-pin SSOP
Commercial, 0° to 85°C
Commercial, 0° to 85°C
Commercial, 0° to 85°C
Commercial, 0° to 85°C
56-pin SSOP – Tape and Reel
56-pin TSSOP
56-pin TSSOP – Tape and Reel
Rev 1.0,November 22, 2006
Page 17 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
